Logic synthesis is a computer process that transforms a circuit description from one level of abstraction to a lower level, usually towards the physical implementation of an integrated circuit. As a result of the logic synthesis process, logic cells or logic functions are arranged physically in multiple circuit rows and/or circuit columns in order to form the completed design. Furthermore, each circuit row and/or circuit column contains multiple logic cells that are arranged adjacent one to another.
Additionally, there may exist gaps or empty spaces between certain adjacent logic cells. These empty spaces, sometimes referred to as “white spaces,” exist in random locations and are of random sizes (i.e., areas) within the circuit design layout. “Filler cells” may be installed within these empty spaces. Filler cells are cells that are added to the design to fill the empty spaces within the circuit rows and/or circuit columns of the original circuit design. A filler cell may include, for example, one or more passive electronic devices, such as resistors or decoupling capacitors, or one or more active electronic devices, such as standard logic gates. Additionally, the size of the physical area of the filler cell determines the scope of functionality that may be incorporated therein. For example, a filler cell of a certain size may allow the incorporation of a decoupling capacitor only or a logic gate only. By contrast, a filler cell of a certain larger size may allow the incorporation of a more complex logic function, such as a gate array, which is a customizable device that is formed of combinatorial or sequential gates. A filler cell that is suitably large to incorporate a gate array is hereinafter referred to as a “customizable filler cell.” A customizable filler cell is of greater use than a standard (i.e., non-customizable) filler cell, as a customizable filler cell provides the circuit designer the opportunity to incorporate circuit changes at any time via a backend release to manufacturing process only, which is a cost effective way to incorporate circuit modifications that may be required in ordered to remedy, for example, a functional problem or a circuit timing problem within the integrated circuit design.
Because the locations, sizes, and number of the empty spaces within a circuit design layout, which is the result of the placement algorithms in the logic synthesis operation, is random, the ability to incorporate customizable filler cells within the overall circuit design is not controlled. In particular, the locations of potential customizable filler cells are not controlled, in that, they may be clustered in one area only of the overall circuit layout or be distributed poorly (e.g., located at the perimeter only of the overall circuit layout). Consequently, the usefulness of the resulting customizable filler cells that exist in random locations, numbers, and distribution within the circuit design, for implementing circuit modifications, is limited. For these reasons, a need exists for a method of optimizing the locations, number, and distribution of customizable filler cells in an integrated circuit physical design process, in order to maximize the opportunity for implementing circuit modifications.